Computing systems often include a memory for storing data and other information in the form of bits. The memory typically includes one or more bit cells or memory cells, and each bit cell is operative to store data in the form of a bit. A memory access control system can control the read and write access to the memory for reading data from and writing data to the bit cells.
FIG. 1 illustrates an exemplary known memory access control system 10 including control logic 12 operatively coupled to a memory 14 for controlling access to memory 14 for read/write operations. Control logic 12 includes software and/or firmware code containing instructions executed on one or more programmable processors (e.g. a central processor unit (CPU)), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), hardwired logic, or combinations thereof. Memory 14 illustratively includes static random access memory (SRAM) 14. Memory 14 includes one or more bit cell arrays 16 each including a plurality of bit cells (i.e., storage cells or memory cells) operative to store data. Each bit cell of bit cell array 16 represents a “bit” of stored data and has two stable states—an off state (e.g., logical “0”) and an on state (e.g., logical “1”).
Control logic 12 initiates a read or write operation upon receiving a read enable signal 42 or a write enable signal 44, such as from other control logic (e.g. operating system) of a processor, for example. Upon determining that a read/write operation is to be performed, control logic 12 outputs a read/write command 32 to memory 14 to initiate the read/write operation.
A read/write driver 18 is operative to write data to bit cell array 16 and to read data from bit cell array 16 based on control signals provided with control logic 12 via communication bus 40. Read/write driver 18 performs read and write operations on bit cell array 16 over a communication bus 38. In particular, communication bus 38 is connected to one or more bit lines of bit cell array 16 (e.g. see bit lines 72, 74 of FIG. 2) to read and write data with bit cell array 16. Read/write driver 18 includes a software or firmware code stored in a memory accessible by control logic 12, and the code contains instructions executable by control logic 12 for reading and writing data to memory 14. In a read operation, read/write driver 18 pulls data from one or more bit cells of bit cell array 16 over communication bus 38. In a write operation, read/write driver 18 writes data to one or more bit cells of bit cell array 16 by selectively causing individual bit cells of array 16 to change state, thereby writing a bit pattern to the bit cell array 16. In one embodiment, read/write driver 18 and control unit 12 are provided in a single chip device (e.g. a processor device), although read/write driver 18 and control unit 12 may alternatively be provided in separate devices.
Memory 14 includes a word line driver 20 operative to drive a voltage VWL of a word line 30 that controls access to one or more bit cells of bit cell array 16. Memory 14 further includes an internal word line decoder 28 (e.g., address decoder) that receives the write/read command 32 from control unit 12 and, in response, provides an inverted word line signal 34 to word line driver 20 of memory 14. Word line decoder 28 alternatively may be external to memory 14. The inverted word line signal 34, illustratively a voltage signal, causes word line driver 20 to output the word line voltage VWL that enables read/write access to some or all bit cells of bit cell array 16. Word line driver 20, which includes logic circuitry, includes an inverter 22 that inverts the inverted word line signal 34 and outputs a non-inverted word line voltage VWL to bit cell array 16.
FIG. 2 illustrates an exemplary known bit cell 50 (i.e., storage cell or memory cell) of the bit cell array 16 of FIG. 1. Four storage transistors 62, 64, 68, 70 of bit cell 50 are coupled together and cooperate to store a bit of data. Two access or pass-gate transistors 54, 56 are provided to control access to bit cell 50 during read and write operations. Transistors 62, 68 are illustratively positive channel field effect transistors (pFETs), and transistors 54, 56, 64, 70 are illustratively negative channel field effect transistors (nFETs), although other transistor types may be used. Transistors 62, 68 are coupled to a supply voltage VDD of bit cell 50 via electrical conductor 52, and transistors 64, 70 are coupled to ground. Bit cell 50 may have other suitable transistor configurations such as, for example, additional or fewer storage transistors for storing data. In the illustrated embodiment, supply voltage VDD is provided from the main memory voltage of memory 14.
Word line 30 of FIGS. 1 and 2 is an electrical path used to transmit the word line voltage VWL to one or more bit cells (e.g., bit cell 50 of FIG. 2) of bit cell array 16 for controlling access to the one or more bit cells. Referring to bit cell 50 of FIG. 2, word line 30 controls the state of access transistors 54, 56 to enable access to the bit cell 50 for read/write operations. Upon transistors 54, 56 being enabled by word line 30 (i.e., by applying the word line voltage VWL), bit cell 50 is electrically connected to bit lines 72, 74 (e.g., electrical conductors) such that the read or write operation can be performed. In particular, write data is provided to bit cell 50 via bit lines 72, 74 during write operations, and data stored at bit cell 50 is read over bit lines 72, 74 during read operations. Bit lines 72, 74 illustratively carry data in the form of a voltage signal that represents logical 0 or 1 (i.e., low or high). While bit cell 50 illustratively includes two bit lines 72, 74 for communicating the data signals BL and BL complement, respectively, a single bit line may be provided in other bit cell configurations.
In operation, upon word line 30 enabling access to bit cell 50 via transistors 54, 56, a read or write operation can be performed via bit lines 72, 74. During a read operation, the stored value Q (e.g., logical 0 or 1) of bit cell 50 stored at node 60 is transferred onto bit line 72, and the inverse of Q stored at node 66 is transferred onto bit line 74. Read/write driver 18 (FIG. 1) then reads the values placed on bit lines 72, 74 via communication bus 38 (FIG. 1). During a write operation, driver 18 places data to be written to bit cell 50 (e.g. logical 0 or 1) on bit lines 72, 74, and bit lines 72, 74 write the data to bit cell 50 at respective nodes 60, 66 upon word line 30 enabling access to bit cell 50 by activating transistors 54, 56.
Word line 30 is operative to enable/disable access to the bit cells 50 of bit cell array 16 (FIG. 1), and a subset of the bit cells 50 of bit cell array 16 may be selected on which to perform the read or write operation. For example, the bit lines (e.g., bit clines 72, 74 of FIG. 2) routed to bit cell array 16 select which bit cells 50 of the array 16 to perform the read/write operation. As such, either a read or write operation may be performed simultaneously on a subset of the bit cells 50 of the array 16. In one embodiment, a read operation may be performed on one subset of bit cells 50 of array 16 on the word line 30 and a write operation may be simultaneously performed on another subset of bit cells 50 of array 16 on the word line 30.
In a typical bit cell 50, the word line voltage VWL of an active word line 30 is set to be substantially equal to the bit cell supply voltage VDD. However, such a configuration can lead to instability in the bit cell 50 due to one or more transistors of the bit cell 50 not being able to hold their states. If a bit cell 50 is unstable during a read or write operation, the state (e.g., logical 0 or 1) of the bit cell 50 may undesirably flip or change, resulting in the bit cell 50 being in an erroneous state.
Some methods directed towards improving the stability of a bit cell 50 have been provided to attempt to reduce unintended state changes of the bit cell 50. One known method directed towards improving bit cell stability in a read operation includes reducing or underdriving the word line voltage VWL to a value below VDD during read and write access. Referring again to the exemplary known system 10 of FIG. 1, word line driver 20 is operative to underdrive word line 30 of bit cell array 16 to attempt to improve the read stability of bit cells of the array 16. In particular, word line driver 20 includes an underdrive circuit 26 including a resistive shunt 24 that is operative to drive the word line voltage VWL of bit cell 50 (FIG. 2) to some voltage level below VDD. Control logic 12 illustratively controls shunt 24 via underdrive enable signal 36 to enable and disable underdriving the word line voltage VWL. When enabled, shunt 24 provides a resistive connection to ground that serves to reduce the likelihood that the output of inverter 22, i.e., voltage VWL, reaches the voltage level of the bit cell supply voltage VDD. In some systems, the resistance of shunt 24 can be small such that the word line voltage VWL is maintained at a small amount (e.g. 50-100 millivolts) below VDD. Shunt 24 can be a transistor device (e.g. transistor 24 of FIG. 4), a resistor, or other suitable resistive device tied to ground.
Referring again to FIG. 2, by underdriving the word line voltage VWL to below VDD, the access transistors 54, 56 become weaker because of the reduced voltage at their gates. At the same time, the respective pull-down transistors 64, 70, which can have a full VDD at their gates, become stronger relative to the access transistors 54, 56. As such, the read stability of bit cell 50 can improve because transistors 64, 70, when stronger than respective access transistors 54, 56, are more likely to hold respective values Q and Q-inverse during a read operation without undesirably flipping states.
In some systems, the word line is only underdriven during a read operation and is driven to VDD during a write operation. For example, in the system 10 of FIG. 1, the underdrive shunt 24 may be disabled during a write operation to allow the word line voltage VWL to remain at about VDD. However, the half-selected or non-selected bit cells of bit line array 16 can become unstable during the write operation when the word line voltage VWL is at about VDD. In particular, during a write operation, often only a subset of the bit cells in bit cell array 16 are written to, as described herein. Half-selected or non-selected bit cells include the bit cells of bit cell array 16 that are not written to during a write operation. These half-selected bit cells of array 16 are thereby electrically configured for a read operation during the write access due to the active word line 30, although read/write driver 18 does not actually read from the half-selected bit cells during the write operation. These half-selected bit cells can become unstable and undesirably change states during the write operation.
For example, referring to FIG. 2, driving the word line voltage VWL at about VDD results in transistors 64, 70 weakening relative to the respective access transistors 54, 56 as compared to underdriving voltage VWL below VDD. As such, a half-selected bit cell 50 can become unstable during the write operation because the transistor 64, 70 may not be able to hold the values at nodes 60, 66 during the write operation, resulting in the bit cell flipping or changing state. As such, the bit data stored at the half-selected cells during a write operation may become corrupt due to the word line 30 being at about VDD.
Other exemplary methods of attempting to improve bit cell read stability may include raising the supply voltage VDD of the bit cell 50 and reducing a pre-charge of the bit line 72, 74. However, these methods also negatively affect the writability of the bit cell 50, potentially leading to undesired state changes and corrupted data.
An exemplary method of attempting to improve bit cell writability includes coupling the bit line (e.g. bit line 72, 74 of FIG. 2) below ground while the word line 30 is underdriven with shunt 24 of FIG. 1. However, complex logic is required to couple the bit lines below ground, resulting in increased complexity and cost of the word line driver 20. Further, the space occupied by logic circuitry (e.g., the write driver 18, etc.) on the integrated circuit is increased due to significantly more transistors and other components required to implement this method.
Therefore a need exists for methods and apparatuses to simultaneously improve both the read stability and the writability of a bit cell. Further, a need exists for such methods and apparatuses to be cost effective and to require minimal chip space.